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preliminary version 6.0 page 1 of 23 features ? tpo true power on functionality ? mono-cell chopped hall system ? tim twisted independent mounting ? dynamic self-calibrating algorithm ? end-of-line programmable switching points ? tc of back-bias magnet programmable ? high sensitivity and high stability of the magnetic switching points ? high resistance to mechanical stress ? digital output signal (voltage interface) ? short-circuit protection ? module style package with two 4.7 nf integrated capacitors general information: the tle4980c is an active hall sensor ideally suited for camshaft applications. its basic function is to map either a tooth or a notch into a unique electrical output state. it has an electrical trimming option for post-fabrication trimming in order to achieve true power on capability even in the case of production spreads such as different magnetic configurations or misalignment. an additional self-calibration module has been implemented to achieve optimum accuracy during normal running operation. it comes in a three-pin package for the supply voltage and an open drain output. psso3-9 programmable true power on hall sensor tle4980c
preliminary version 6.0 page 2 of 23 functional description: the basic operation of the tle4980c is to map a ?high positive? magnetic field (tooth) into a ?low? electrical output signal and to map a ?low positive? magnetic field (notch) into a ?high? electrical output. optionally the other output polarity can be chosen by programming the prom. a magnetic field is considered as positive if the north pole of a magnet shows towards the rear side of the ic housing. since it seems that also backbias-reduced magnetic configurations still show significant flux densities in one distinct direction the circuit will be optimised for one flux direction in order to provide an optimal signal to noise behaviour. for understanding the operation of the tle4980c three different modes have to be considered: initial operation after power up: this mode will be referred to as ?initial mode?. operation following the initialisation before having full information about the target wheel: this mode will be referred to as ?precalibrated mode?. normal operation with running target wheel: this mode will be referred to as ?calibrated mode?. initial mode: the magnetic information is derived from a chopped hall amplifier. the threshold information comes from a prom-register that may be programmed at any time, but only once (no eeprom). the magnetic information is compared against the threshold and the output state is set correspondingly. some hysteresis is introduced in order to avoid false switching due to noise. in case that there is no prom-value available (prom has not been programmed before) the chip starts an auto-search for the actual magnetic value. the initial threshold value is set to this magnetic value. this feature can be used to find a tpo-value for providing correct programming information to the chip simply by setting the chip in front of a well-defined static target. in this case a moving target wheel is not necessary. in case there is a prom value available, the open drain output will be turned on or off by comparing the magnetic field against the pre-programmed value. during rotation of the target wheel a self-calibration procedure is started in the background. the ic memorises magnetic field values for adjusting the threshold to an optimum value. the exact way of threshold adjustment is described in more detail in the precalibrated mode. once the ic has sufficient information for improving the accuracy (typically after 2-3 teeth) the device threshold value is adjusted and the device is switched into the precalibrated mode. precalibrated mode: in the precalibrated mode the ic permanently monitors the magnetic signal. to say it in more detail, it searches for minimum (caused by a notch) and maximum (caused by a tooth) values in the signal. once the ic has found a pair of min / max values it calculates the optimum threshold level and adjusts the system offset in such a way, that the switching occurs on this level. the threshold adjustment is limited to increments of approx. 1,5mt per calibration in order to avoid totally wrong information caused by large signal disturbances (emc-events or similar). the optimum threshold level may differ depending on the target wheel. for example, for regular gearwheels the magnetic signal
preliminary version 6.0 page 3 of 23 is close to a sinusoid and the optimum threshold value can be considered as 50% value, which is the mean value between minimum and maximum signal. for camshaft wheels an optimum threshold may be at a different percent-value in order to have minimum phase error over airgap variations. see fig.4 for definition of this dynamic switching level. in case that the initial prom-value does not lead to a switching of the ic because it is slightly out of the signal range the ic nevertheless does its switch value correction in the background. after having corrected for a sufficient amount the ic will start its output switching. the output switching includes some hysteresis in order to avoid false switching. if the ic has not been programmed yet, it uses the default 50% value between the minimum and the maximum as switching level. calibrated mode: after a certain number of switching events (64) the accuracy is considered to be quite high. at this time the chip is switched into an averaging mode (= calibrated mode) where only minor threshold corrections are allowed. in this mode a period of 32 switching events is taken to find the absolute minimum and maximum within this period. threshold calculation is done with these minimum and maximum. a filter algorithm is implemented, which ensures that the threshold will only be updated, if the adjustment value calculated shows in the same direction over the last four consecutive periods. every new calculated adjustment value that shows in the same direction causes an immediate update of the threshold value. if the direction of the calculated adjustment value changes, there must be again four consecutive adjustment values in the same direction for another update of the threshold value. additionally there is an activation level implemented, allowing the threshold to be adjusted only if a certain amount (normally bigger than 1lsb) of adjustment is calculated. the threshold correction per cycle is limited to 1 lsb. the purpose of this strategy is to avoid larger offset deviations due to singular events. also irregularities of the target wheel are cancelled out, since the minimum and maximum values are derived over at least one full revolution of the wheel. the output switching is done at the threshold level without visible hysteresis in order to achieve maximum accuracy. nevertheless the chip has some internal protection mechanisms in order to avoid multiple switching due to noise. changing the mode: every time after power up the chip is reset into the initial mode. subsequent modes (precalibrated, calibrated) are entered consequently as described before. in addition, two plausibility checks are implemented in order to enable some self-recovery strategy in case of unexpected events. first, there is a watchdog, which checks for switching of the sensor at a certain lower speed limit. if for 12 seconds there is no switching at the output, the chip is reset into the initial mode. second, the ic checks if there is signal activity seen by the digital logic and at the same time there is no switching at the output. if the digital circuitry expects that there should have been 4 switching events and actually no switching has occurred at the output, the ic is reset into the initial mode.
preliminary version 6.0 page 4 of 23 reset: there are several conditions, which can lead to a reset condition. for the ic behaviour we have to distinguish between a ?output hold mode?, a ?long reset?, a ?short reset? and a ?software reset?. output hold mode: this operating mode means that the output is held in the actual state and there is no reset on the digital part performed. this state will be released after the ic reaches his normal operation condition again and goes back into the operating mode he was before. the following conditions lead to the output hold mode: ? a drop in the supply voltage to a value less than 2.4v but higher than 2.0v for a time not longer than 1s .. 2s. long reset: this reset means a total reset of the analogue as well as for the digital part of the ic. the output is forced to its default state (?high?). this condition remains for less than 1ms. after this time the ic is assumed to run in a stable condition and enters the initial mode where the output represents the state of the target wheel (prom value). the following conditions lead to a long reset: ? power-on condition. ? low supply voltage: drop of the supply voltage to values less than 2.4v for a time longer than 1s .. 2s or drop of the supply voltage to values less than 2.0v. short reset: this reset means a reset of the digital circuitry. the output memorizes the state he had before the reset. this condition remains for approx. 1s. after that time the chip is brought into the initial mode (output stays ?high? for approx. 200s for an untrimmed ic). then the output is released again and represents the state of the target wheel (prom value). the following conditions lead to a short reset: ? watchdog overflow: if there is no switching at the output for more than 12 seconds. ? if there are four min- or max-events found without a switching event at the output software reset: this reset can be performed in the testmode through the serial-interface. the ic output is then used as data output for the serial interface. the following condition lead to a software reset: ? there is a reset applied through the serial interface
preliminary version 6.0 page 5 of 23 table 1 shows an overview over the behaviour of the output under certain conditions. unprogrammed programmed noninverted inverted noninverted inverted output hold mode q n-1 -q n-1 q n-1 long reset high - high high short reset high - normal tpo inverted tpo initial mode high (self calibration) - normal tpo inverted tpo precalibrated mode normal - normal inverted calibrated mode normal - normal inverted q n-1 ? state of output before a reset occurs normal tpo ? ?low? if b > b tpo ; ?high? if b < b tpo inverted tpo ? ?high? if b > b tpo ; ?low? if b < b tpo normal ? ?low? if b > b threshold ; ?high? if b < b threshold inverted ? ?high? if b > b threshold ; ?low? if b < b threshold table1: output behaviour under certain conditions hysteresis concept: there are two different hysteresis concepts implemented in the ic. the first one is called visible hysteresis , meaning that the output switching levels are changed between two distinct values (depending on the direction of the magnetic field during a switching event), whenever a certain amount of the magnetic field has been passing through after the last switching event. the visible hysteresis is used in the initial mode. see fig.1 for more details. the second form of hysteresis is called hidden hysteresis . this means, that one cannot observe a hysteresis from outside. if the value of the switching level does not change, the output always switches at the same level. but inside the ic there are two distinct levels close above and below the switching level, which are used to arm the output. in other words if the value of the magnetic field crosses the lower of this hysteresis levels, then the output will be able to switch if the field crosses the switching level. after this switching event the output will be disabled until the value of the magnetic field crosses one of the two hysteresis levels. if it crosses the upper hysteresis level, then the output will be armed again and can switch if the magnetic field crosses the switching level. on the other hand, if the magnetic field does not reach the upper hysteresis level, but the lower hysteresis level will be crossed again after a switching event, then the output is allowed to switch, so that no tooth will be lost. but please notice that this causes an additional phase error. the hidden hysteresis is used in the precalibrated and calibrated mode. for more details see fig.2
preliminary version 6.0 page 6 of 23 t b b b off b on b tpo b hys t q fig. 1: visible hysteresis (initial mode)
preliminary version 6.0 page 7 of 23 t b b b off b on b cal b hys /2 t q fig. 2: hidden hysteresis (precalibrated and calibrated mode)
preliminary version 6.0 page 8 of 23 block diagram: the block diagram is shown in fig.3. the ic consists of a spinning hall probe (monocell in the centre of the chip) with a chopped preamplifier. next there is a summing node for threshold level adjustment. the threshold switching is actually done in the main comparator at a signal level of ?0?. this means, that the whole signal is shifted by this summing node in that way, that the desired switching level occurs at zero. this adjusted signal is fed into an a/d-converter. the converter feeds a digital calibration logic. this logic monitors the digitised signal by looking for minimum and maximum values and also calculates correction values for threshold adjustment. the static switching level is simply done by fetching a digital value out of a prom. the dynamic switching level is done by calculating a weighted average of min and max value. for 50% weighting factors are equal, for other values weighting factors are different. for example, a factor of approximately 67% can be achieved by doubling the weight of the max value. generally speaking, a threshold level of b cal = b min + (b max ? b min ) * k 0 can be achieved by multiplying max with the switching level k 0 and min with (1-k 0 ). serial interface: the serial interface is used to program the chip. at the same time it can be used to provide special settings and to read out several internal registers status bits. the interface description consists of a physical layer and a logical layer. the physical layer describes format, timing and voltage information, whereas the logical layer describes the available commands and the meaning of bits, words and addresses. physical interface layer : the data transmission is done over the vs-pin, which generates input information and clock timing, and the out-pin q, which delivers the output data. generally the interface function is disabled; this means, that in normal operation including normal supply distortion the interface is not active and therefore the chip operates in its normal way. a special initialisation sequence must be performed to enter the interface mode that is also referred to as ?testmode?. for an untrimmed chip (this is a chip which has not been programmed yet) the initialisation sequence is quite simple: for a short time after power on or reset the chip monitors the output signal. the internal logic brings the output into a high impedance state, which will be a logical ?high? caused by the external pull-up resistor. if now the chip sees a logical ?low? (for at least 1ms), which is an output voltage lower than 0.3v, the chip enters the testmode. for programmed chips this initialisation procedure is not possible. instead a second initialisation mechanism has been implemented which is always valid. this means, that using this mechanism the chip will always enter the test mode even in normal operation. the test mode will be disabled after the ic has been programmed. since you have to be in test mode while programming the ic, you can read out the programmed values as long as you do not leave the test mode. the initialisation procedure for this second mode is as follows: whenever the output signal is ?low? the external supply has to be set to more than 7v (nom. 7.5v). whenever the output signal is ?high? the external supply has to be set to less than 5v (nom. 4.5v). this has to be done for at least 5 consecutive periods. the delay between the output signal and the modulated supply signal must not exceed fourty periods of the internal
preliminary version 6.0 page 9 of 23 clock (less than 20s delay). any disturbance in this sequence will terminate the initialisation procedure. after having successfully finished the initialisation the chip enters the testmode and data transmission can be started. data transmission: serial transmission is done in words (lsb first). a logical ?1? is represented by a long (2/3 of one period) ?high? voltage level (higher than 5v) on the supply followed by a short (1/3 of one period) ?low? voltage level (lower than 5v), whereas a logical ?0? is represented by a short ?high? level on the supply followed by a long ?low? level. at the same time this high/low voltage combination, which forms in fact a bit, acts as a serial interface clock which clocks out logical high / low values on the output. we recommend a period length of around 100s per bit. see fig.5 for a more detailed timing diagram. end of word is indicated by a long (we recommend longer than 200s, first 30s should be higher than 5v and the rest lower than 5v) ?low? supply. please note, that for communicating 13 bits of data 14 vs-pulses are necessary. if more than 14 input bits are transmitted the output bits are irrelevant (transmission buffer empty) whereas the input bits remain valid and start overwriting the previously transmitted bits. in any case the last 14 transmitted bits are interpreted as transmitted data word (13 bits) + 1 stop bit. end of communication is signalled by a long ?high? voltage level. a new communication has to be set up by a new initialisation sequence. programming the prom: one possibility for programming the static threshold value is to run the ic on a testbench (or in the car), to wait until the ic has reached the calibrated mode and then simply to issue the copy commands, which transfers the calibrated threshold value into the prom. use the following procedure for this type of programming: 1) apply an oscillating magnetic field with a suitable offset (notice that for unfused devices this offset lies in the middle of the maximum and minimum value of the magnetic field). 2) enter the testmode with the second procedure described in the chapter ?physical interface layer?. 3) wait until the ic has reached the calibration mode. 4) choose a k-factor and supply 12v to the output. 5) write the three following bit-combinations via the serial interface: 1010k 6 k 5 k 4 k 3 k 2 k 1 k 0 i1 1011k 6 k 5 k 4 k 3 k 2 k 1 k 0 i1 1011111111111 here k i indicate the 7bits of the k-factor (k 6 ? msb and k 0 ? lsb) in dual-code. this means: 1100000 is equal to k 0 =0.75 and 1010010 is equal to k 0 =0.65. the bit i is the so called inverting bit, which determines either the output switches inverse to the applied magnetic field (i=?0?) or not (i=?1?). 6) leave the testmode by writing a long ?high? voltage level. a second form of programming the static threshold value is to bring the ic in front of a target, which delivers a static magnetic field with a suitable strength and perform a
preliminary version 6.0 page 10 of 23 power on by forcing the output to a low state for at least 1ms. this brings the chip in the testmode and he starts immediately a successive approximation and adjusts the value of the offset-dac to the switching level that corresponds to the field strength. use the following procedure for this type of programming: 1) apply a static magnetic field with a suitable strength. 2) enter the testmode with the first procedure described in the chapter ?physical interface layer?. 3) wait until the ic has made the successive approximation and reached the right level for the offset-dac (at least 10 periods of the internal clock frequency after releasing the output). 4) choose a k-factor and supply 12v to the output. 5) write the three following bit-combinations via the serial interface: 1010k 6 k 5 k 4 k 3 k 2 k 1 k 0 i1 1011k 6 k 5 k 4 k 3 k 2 k 1 k 0 i1 1011111111111 here again k i indicate the 7bits of the k-factor (k 6 ? msb and k 0 ? lsb) in dual- code. this means: 1100000 is equal to k 0 =0.75 and 1010010 is equal to k 0 =0.65. the bit i is the so called inverting bit, which determines either the output switches inverse to the applied magnetic field (i=?0?) or not (i=?1?). 6) leave the testmode by writing a long ?high? voltage level. it has to be noted that the chip has increased power dissipation during programming for blowing the fuses. the additional power is taken out of the output. overvoltage protection: the process used for production has a breakthrough voltage of approximately 27.5v. the chip can be brought into breakthrough without damage if the breakthrough power (current) is limited to a certain value. usually destruction is caused by overheating the device. therefore for short pulses the breakthrough power can be higher than for long duration stress. for example for load dump conditions an external protection resistor of 200 ? is recommended in 12v-systems and 50 ? in 5v-systems.
preliminary version 6.0 page 11 of 23 offset dac main comp digital spinning hall probe chopper & filter + - out n-channel open drain actual switching level min max algorithm prom k-factor inv. bit b tpo analog supply digital supply hall suppl y overtemperature & short-circuit protection supply regulator bias for temperature & technology compensation hyst comp gnd clamping clamping & reverse voltage protection interface reset oscillator vs fig.3: blockdiagram of tle4980 enable tracking adc
preliminary version 6.0 page 12 of 23 switching value b cal (threshold) maximum value (b max ) minimum value (b min ) b cal = b min + (b max ? b min ) x k 0 fig. 4: dynamic threshold value true power on value (b tpo ) calibration b t data (vs) fig. 5: serial protocol input output data (q) 11100011 stop bit 00100010 lsb msb lsb msb undefined
preliminary version 6.0 page 13 of 23 absolute maximum ratings: symbol name min typ max unit note v s supply voltage -18 18 v -24 24 v 1h with r series >=200 ? 1 -26 26 v 5min with r series >=200 ? i v q output off voltage -0.3 18 v -0.3 24 v 1h with r load >=500 ? -0.3 26 v 5min with r load >=500 ? -1.0 v 1h v q output on voltage 16 v current internal limited by short circuit protection (72h@t a <40c) 18 v current internal limited by short circuit protection (1h@t a <40c) 24 v current internal limited by short circuit protection (1min@t a <40c) i q continuous output current -50 50 ma t j junction temperature -40 c 155 c 2000h (not additive) 165 c 1000h (not additive) 175 c 168h (not additive) 195 c 3x1h (additive to the other life times) r thja thermal resistance junction-air 190 k/w t s storage temperature -50 150 c b magnetic field induction mt no limit v esd esd - protection 4 kv according to standard eia/jesd22-a114-b hbm note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 accumulated life time
preliminary version 6.0 page 14 of 23 electro magnetic compatibility - (values depend on r series ) ref. iso 7637-1; test circuit of figure 6 ; ? b pp = 2mt (ideal sinusoidal signal); v s =13.5v 0.5v, f b = 1khz; t= 25c; r series 200 ?; parameter symbol level/typ status testpulse 1 testpulse 2 testpulse 3a testpulse 3b testpulse 4 testpulse 5a v ld iv / -100v iv / 100v iv / -150v iv / -300v iv / 100v - ii / 55v iii / 70v c 1 c a c a - 2 c e ref. iso 7637-3; test circuit of figure 6 ; ? b pp = 2mt (ideal sinusoidal signal); v s =13.5v 0.5v, f b = 1khz; t= 25c; r series 200 ? ; no. parameter symbol level/typ status 1.2.2 testpulse 1 testpulse 2 testpulse 3a testpulse 3b v ld - / - - / - iv / -300v iv / 300v - - a a note: test criteria for status c: no missing pulse no additional pulse on the ic output signal. test criteria for status a: same plus duty cycle and jitter in the specification limits. test criteria for status e: destroyed note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 according to 7637-1 the supply switched ?off? for t=200ms. for battery ?on? is valid status ?a? 2 according to 7637-1 the test voltage for test pulse 4 is 12v 0.2v
preliminary version 6.0 page 15 of 23 figure 6: testcircuit for emc-tests v emc r series v s gnd q r load 1 k ? ? ? ? c load 50 pf 5v 200 ? ? ? ?
preliminary version 6.0 page 16 of 23 operating range: symbol name min max unit note v s operating supply voltage 3.3 18 v continuous 24 v 1h with r series >=200 ?; extended limits for parameters in characteristics t j operating junction temperature -40 c 155 c 2000h (not additive) 165 c 1000h (not additive) 175 c 168h (not additive) t cal trimming temperature 15 35 c v s =5/12v i q continuous output on current 020mav qmax =0.5v v q continuous output off voltage -0.3 18 v continuous -18 24 v 1h with r load >=500 ? f b magnetic signal switching frequency 0 5 khz measured between two rising edges of the magnetic signal t edge rise time of magnetic edge 85 s the edge of the magnetic signal is not allowed to rise faster than this value (otherwise the tracking adc of the chip is not able to follow) b linear magnetic range 0 120 mt b bb magnetic preinduction 20 70 mt b tpo true power on range 20 75 mt hysteresis not included (typ. b hys =1.0mt) b a ctpo magnetic signal swing for tpo-function 5.8 50.0 mt pp b tpo =44mt; b hys = 0.75mt 1 b ac_cal magnetic signal swing for calibrated mode 350mt pp b over magnetic overshoot 10 % of b ac_cal k 0 adjustment range of switching level 10 90 % of b ac_cal the switching point in calibrated mode is determined by: b cal = b min + (b max ? b min ) * k 0 tc magnet magnet temperature coefficient -1200 -500 ppm/k 1 encapsulated devices with b tpo =44mt and b hys =0.5mt show minimum value of 5mt pp
preliminary version 6.0 page 17 of 23 ac/dc characteristics: symbol name min typ max unit note v qsat output saturation voltage 0.25 0.5 v i q = 20ma i qleak output leakage current 0.1 10 a v q = 18v i qshort current limit for short circuit protection 30 50 80 ma t prot junction temperature limit for output protection 195 210 230 c t rise 1 output rise time 4 11 17 s v load = 4,5..24v r load = 1k ? c load = 4,7nf included in package t fall 2 output fall time 0.4 0.8 s v load = 4,5..24v r load = 1k ? c load = 4,7nf included in package i svmin supply current @ 3.5v 5.5 6.5 ma v s = 3.5v i s supply current 5.6 7.5 ma i smax supply current @ 24v 8.0 ma r series >=200 ? v sclamp clamping voltage v s -pin 27.5 v 1ma through clamping device v qclamp clamping voltage q-pin 27.5 v 1ma through clamping device 0.56 3 1ms t on power on time 0.75 5 ms time to achieve specified accuracy. during this time the output is locked 4 t d 6 delay time of output to magnetic edge 6 10 14 s higher magnetic slopes and overshoots reduce t d , because the signal is filtered internal. 7 ? t d temperature drift of delay time of output to magnetic edge -3 3 s not additional to t d t watch watchdog time 12 s if there is no change at the output during this time a reset is performed. n watch watchdog edges 4 - if n watch min or max-events have been found and there was no change at the output a reset is performed. 1 value of capacitor: 4.7nf 10% (excluded drift due to temperature); ceramic: x7r; maximum voltage: 100v 2 see footnote 1 3 trimmed ic 4 output is in high-state 5 untrimmed ic 6 measured at t j = 25c; represents the influence of the production spread (corresponds to the 3 -value) 7 measured with a sinusoidal-field magnetic-field with an amplitude of 10mt and a frequency of 1khz
preliminary version 6.0 page 18 of 23 symbol name min typ max unit note f clk clock frequency for digital part 1.76 mhz f chopper clock frequency used by the chopper preamplifier 220 khz output jitter is not affected by the chopper frequency ? k 0 resolution of switching level adjustment 0.8 % fsr odac full scale range of the offset-dac 90 120 150 mt fsr odactyp full scale range of the offset-dac 104 120 141 mt t j =25c b tpo_res resolution of threshold in tpo mode 0.12 mt ? b tpo drift of b tpo -point -1.8 +3.2 mt b tpo =44mt 1 ? b ac_cal accuracy of threshold in calibration mode -2 2 % percentage of b cal ; b ac =10mt pp sinusoidal signal 2 ; systematic deviation due to hysteresis in the filter algorithm of 1.5% at b ac =10mt pp not included; b neff effective noise value of the magnetic switching points 33 t t j = 25c; the magnetic noise is normal distributed, nearly independent to frequency and without sampling noise or digital noise effects. the effective value corresponds to 1 probability of normal distribution. consequently a 3 value corresponds to 0.3% probability of appearance. 55 120 t typical value corresponds to 1 . max value corresponds to 1 = values in the full temperature range and include technological spreads. note: the listed ac/dc and magnetic characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not other specified, typical characteristics apply at t j = 25 c and v s = 12 v. 1 this value shows the deviation from the programmed b tpo value and its temperature coefficient. included are the package-effect, the deviation from the adjusted temperature coefficient of the b tpo point (resolution of the temperature coefficient and spread of the technologie) and the drift of the offset (over temperature and lifetime). not included is the hysteresis in the initial mode. 2 bigger amplitudes of signal lead to smaller values of ? b ac_cal
preliminary version 6.0 page 19 of 23 package dimensions p-sso 3-9 ( p lastic s ingle s mall o utline)
preliminary version 6.0 page 20 of 23 position of the hall element
preliminary version 6.0 page 21 of 23 tape loading orientation pin definitions and function psso3-9 pin symbol function 1 v s supply voltage 2 gnd ground 3 q open drain input
preliminary version 6.0 page 22 of 23 appendix: calculation of mechanical errors: ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? magnetic signal output signal figure 7: systematic error ? ? ? ? and stochastic error ? ? ? ?? ? ? ? systematic phase error ? ? ? ? the systematic error comes in because of the delay-time between the threshold point and the time when the output is switching. it can be calculated as follows: d t n ? ? = 60 360 ? ? ... systematic phase error in n ... speed of the camshaft-wheel in min -1 t d ... delay time (see specification) in sec
preliminary version 6.0 page 23 of 23 noise 1 bneff_typ bn_max 3 b ? ? ? ? ? ? ? b phase-jitter figure8: phase-jitter stochastic phase error ?? ?? ?? ?? the stochastic phase error includes the error due to the variation of the delay time with temperature and the error caused by the resolution of the threshold. it can be calculated in the following way: d d t n ? ? ? = ? 60 360 ? cal ac cal b b _ ? ? ? ? = ? ? ? ?? d === ... = stochastic phase error due to the variation of the delay time over temperature in ?? cal ... stochastic phase error due to the resolution of the threshold value in n ... speed of the camshaft wheel in min -1 b ? ? ? ... inverse of the magnetic slope of the edge in / t ? t d ... variation of delay time over temperature in sec ? b ac_cal ... accuracy of the threshold in t jitter (repeatability) the phase jitter is normally caused by the analogue system noise. if there is an update of 1bit of the offset-dac due to the algorithm, what could happen after a period of 16 teeth, then an additional step in the phase occurs (see description of the algorithm). this is not included in the following calculations. the noise is transformed through the slope of the magnetic edge into a phase error. the phase jitter is determined by the two formulas: () typ neff typ jitter b b _ _ ? ? ? = ? ? () max _ max _ n jitter b b ? ? ? = ? ?
preliminary version 6.0 page 24 of 23 ? jitter_typ ... typical phase jitter at t=25c in (1sigma) ? jitter_max ... maximum phase jitter at t=170c in (3sigma) b ? ? ? ... inverse of the magnetic slope of the edge in / t b neff_typ ... typical value of b neff in t (1 -value at t=25c) b n_max ... maximum value of b n in t (3 -value at t=170c) example: assumption: n = 3000 min -1 t d = 14 s ? t d = 3 s ? ? ? b = 1 mt/ ? b ac_cal = 0.2 mt (=2% of 10mt swing) b neff_typ = 33 t (1 -value at t=25c) b n_max = 360 t (3 -value at t=170c) calculation: ? = 0.252 ... systematic phase error ?? d = 0.054 ... stochastic phase error due to delay time variation ?? cal = 0.2 ... stochastic phase error due to accuracy of the threshold ? jitter_typ = 0.033 ... typical phase jitter (1 -value at t=25c) ? jitter_max = 0.36 ... maximum phase jitter (3 -value at t=170c)

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